IBM Mainframe Forum

bobguo wrote:... i don't know the meaning of 'R'(within your sentence 'In the R form GETMAIN macro')

The GETMAIN (and FREEMAIN) macros have one positional parameter: GETMAIN R,keyword parameters. This positional parameter is called - don't ask why, 'cause I don't know - the "form" of the GETMAIN or FREEMAIN macro. The R form goes back to OS/360, and may imply "register" since only registers convey the parameters to the SVC service that performs the request. Other OS/360 variants of the macro pass parameter data through a parameter list and use a different SVC.

In any event, the question was, why is BAL 1,*+4 used? Actually, I cheated a little bit; I didn't tell you the R form of the FREEMAIN macro which uses the same SVC as the R form of the GETMAIN macro, sets the high order 8 bits of register 1 to 0. A little more background: in OS/360 three different SVCs are used for storage management. SVC 4 is GETMAIN with some sort of parameter list, SVC 5 is FREEMAIN with some sort of parameter list, and SVC 10 is GETMAIN and FREEMAIN with parameters passed to it in registers 0 and 1. MVS added a fourth SVC for GETMAIN and FREEMAIN. At some point the STORAGE macro was added, which uses the PC instruction rather than the SVC instruction.

Another useful tool is MVS Diagnosis: Reference for your z/OS release. It has chapters like "SVCs and associated macros" and "SVC descriptions," with a sub chapter for each SVC. If you check SVC 10 you can find out what is in register 1. Once you know what it expects in register 1 you then have to figure out how the BAL sets register 1, which I have sort of laid out for you already in this topic. A little quality time spent with Principles of Operation and MVS Diagnosis: Reference should enable you to answer the question.

I have known the answer for many years, in part because a friend of mine working on another program got into trouble because he didn't really know the answer to this very question and I had to dig up the answer.

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bobguo (Fri Oct 25, 2013 2:40 pm)

In 24-bit mode:

BAL Rx,*+4
BALR Rx,Ry

The hardware execution of BAL(R) in 24-bit mode actually gated the right-hand half of the PSW into Rx. This gives you the address in bytes 1-3 of Rx and also you get the ILC/CC/Program Mask bits into byte 0. The ILC in bits 0-1 of Rx is of no real interest, but Rx would have the current Condition Code in bits 2-3 so that your could preserve it. Also you got the current Program Mask in bits 4-7 of Rx if you wanted to know/save it.

BAS(R) sets bits 0-7 to 0. The '0' in bit 0 is meant to indicate that the called is in '24' bit mode.

In 31-bit mode:

you get '1' in bit 0, and the address in bits 1-31. The '1' is meant to indicate that the called is in '24' bit mode.

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The setting of '0' and '1' in bit 0 is used by BSM return sequences to indicate returning in 24 or 31 bit mode.
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Short quiz: In the latest IBM CPUs there are over 1300 instructions. Do you know them all?

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bobguo (Fri Oct 25, 2013 2:40 pm)

Re my prior post:
"you get '1' in bit 0, and the address in bits 1-31. The '1' is meant to indicate that the called is in '24' bit mode."

should read:

you get '1' in bit 0, and the address in bits 1-31. The '1' is meant to indicate that the called is in '31' bit mode.

first of all, thank you very much for your help.

today,i thought i got why DCB must reside below the line and something else.
i referred to the expansion of macro OPEN:


and the chapter of "SVC descriptions" of the book MVS Diagnosis: Reference, AL1(128) can tell me this file was opened as input, AL3(FILEIN) tells FILEIN must reside below the line, because the length of this address variable is 3, which can't contain 31 bits.
after BAL executed, R1 points to the first address of parameter's address list, and then it was used as input to call module IGC0001I which 'SVC 19' indicates.

thank you again!

TallBob wrote:IShort quiz: In the latest IBM CPUs there are over 1300 instructions. Do you know them all?

No. Too d**** many!

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bobguo (Fri Oct 25, 2013 5:37 pm)

bobguo wrote:first of all, thank you very much for your help.

today,i thought i got why DCB must reside below the line and something else.
i referred to the expansion of macro OPEN:

Select all

 8          OPEN (FILEIN,(INPUT)) 
 9+         CNOP  0,4             
10+         BAL   1,*+8           
11+         DC    AL1(128)         
12+         DC    AL3(FILEIN)     
13+         SVC   19           

...

And don't forget DCBDEBAD, DCBEODAD, DCBSYNAD, DCBEXLST, DCBBUFCB, and DCBGET/DCBPUT/DCBREAD/DCBWRITE and others. All of them are AL1(flags),AL3(address). DCBDCBE is A(address), and the only exception to the rule.

under 31bits, what can we do to ensure DCBs would be resided below the line when we are coding?
or there is no need for us to care about it, all the DCBs would be resided below the line automatically by the system?

bobguo wrote:under 31bits, what can we do to ensure DCBs would be resided below the line when we are coding?
or there is no need for us to care about it, all the DCBs would be resided below the line automatically by the system?

The topic DCB and APF Authorized in this forum discusses several methods an RMODE ANY/AMODE 31 program can use to place a DCB below the line for use by the program. The original poster's program in that topic failed because he unintentionally had a reentrancy violation. It is not automatic; the program must do this.

This is an example.

this is one sample one with S0C4 abend.
if 'RMODE ANY' was changed to 'RMODE 24', it runs okay.
if it was changed to 'RMODE 31', it keep hitting S0C4.

RMODE ANY which means '24/31bit reside mode' are all suitable to run. here, why it was resided under 31bit instead of 24bit?

my another question is: if i hit errors like this in the future, where can i refer to confirm it was rmode/amode error?

1. The program you show will not link edit without errors. The OPEN, CLOSE and DCB macros all have 24-bit address constants.
2. RMODE ANY is just what it says. What is not said is storage above the line is preferred. It will load and run fine below the line if no above the line storage is available.
3. Debugging. Sadly, there's a lot of guess work.
   • Check the ABEND. S0C4 often indicates an AMODE issue.
   • Check the AMODE bit in the PSW.
   • Locate the base register / base registers in the failing instruction. If there are bits on in the high order byte and you're in AMODE 24, oops. On the other hand, an AMODE 31 the program could have loaded an AL3 address with flags in the high order byte. For example L x,DCBDEBAD will give you trouble. I always follow something like that with N x,=A(X'FFFFFF') even in 24-bit programs.

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bobguo (Thu Oct 31, 2013 9:49 am)