IBM Mainframe Forum

Hello Experts,

I have the below code in one of my programs and am finding it difficult to understand on when exactly it would branch to SETCONFL



Below is my understanding of the above instructions...

As far as I understand the below 'TEST UNDER MASK" instruction would always set the Condition Code to 0 as the Mask bits are 0.



Now coming to the 2nd instruction,condition code is 0000 from above and the mask bits is 0101(binary for 5)..So It doesnt look like the branch will ever take place as there is no on-bit on condition code





Can you please correct me where I got this wrong?

Thanks,
Ram Kumar

ramkumar1992sp wrote:Hello Experts,

I have the below code in one of my programs and am finding it difficult to understand on when exactly it would branch to SETCONFL

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XXXXBITS TM    0(R5),X'00'                  TEST ARRAY FOR CONFLICT    
         BC    5,SETCONFL                        
 

Below is my understanding of the above instructions...

As far as I understand the below 'TEST UNDER MASK" instruction would always set the Condition Code to 0 as the Mask bits are 0.

That is correct.

Where you are going wrong is understanding the relationship between the condition code value and the condition mask in the BC instruction.
When you specify multiple bits in the mask, the instruction will branch if the condition code matches any of the bits in the mask. For example if you specify 1010 (A or 10) the instruction will branch if the condition code is 00 or 10. Your BC 5 (0101) will not branch because the condition code is 0; it will branch if the condition code is 1 or 3.

It can be most confusing. Just yesterday I did a TM byte,8/BC 8,xxx. The code took the branch, though I was convinced the bit was off. It took me the better part of three hours before I realized I was testing the wrong byte!

These users thanked the author steve-myers for the post:

ramkumar1992sp (Mon Sep 12, 2016 6:51 pm)

Thanks Steve for helping me understand how BC instruction works.But it still looks like there would be no branch as the condition code is always 0 ..do you see any circumstance where it would branch to SETCONFL ?

Thanks,
Ram Kumar

It's not really possible to answer the query with what has been presented so far, or you have not done enough checking before posting the query. For example, 16(R4) could already be Y before the test.

Hi Steve,

I'm sorry about not getting back to this much earlier.I had to complete a different project before getting back to this conversion project.

As far as I understand about the TM and the BC instrcution,I dont see how it would branch to SETCONFL.

For example, 16(R4) could already be Y before the test

I checked this and dont see the FLAG being set anywhere else..But my question is how would it branch.So far I'm not understanding how the branch would occur.

Is there some possibility that TM would return a condition code of 1 or 3 even though the mask bits are zeroes ? Could the contents of 0(R5) affect it ?

Please help.


Thanks,
Ram Kumar

There is very little we can do. You have to do more research.

For example: Is the instruction modified before it is executed? This is rarely done these day, but ...

MVI XXXXBITS+1,B'01101000'
...
XXXXBITS TM ...,X'00'

The mask I set is purely arbitrary; I chose it because it it not X'00'.

A BC mask 5 after a TM will usually branch; like most Assembler programmers I don't have the condition code settings memorized and just used the extended branch instruction: BZ(8), BNZ (7), BO(1), BNO (14). Since TM never sets CC = 2, BC 5 is more or less equivalent to BNZ.

I also thought about using the EX instruction; e.g. something like

LA14,B'01101000'
EX 14,XXXXBITS

I rejected that notion when I remembered the BC 5 immediately after the XXXXBITS TM ...,X'00' instruction.

I'm afraid I'm out of ideas.

These users thanked the author steve-myers for the post:

ramkumar1992sp (Mon Nov 21, 2016 7:40 pm)

Thanks Steve.

I see the instruction is modified using Register RB before the TM instruction is executed.This isn't a new program.It looks like it was written in 1972.

When the TM instruction is executed,aren't we checking the contents of RB register against the mask bits of zeroes.How is the value of XXXXBITS affecting it ?




Thanks,
Ram Kumar

The assembler generates 91005000 as the code for the TM instruction. Moving 1(RB) to XXXXBITS+1 means the 00 in the code has been changed -- so you CANNOT think that the test is against X'00'. The test is actually against whatever byte is at 1(RB).

These users thanked the author Robert Sample for the post:

ramkumar1992sp (Mon Nov 21, 2016 8:50 pm)

When the TM instruction is executed,aren't we checking the contents of RB register against the mask bits of zeroes.

nope, the TM is using as mask the content of the storage location addressed by R8 + 1
( the 00 of the instruction is overwritten by the move )

These users thanked the author enrico-sorichetti for the post:

ramkumar1992sp (Mon Nov 21, 2016 8:50 pm)

Thanks for the response Robert and Enrico.

So now, is the TM instruction the below way ?



I havent understood this completely.Is it that X'00' and XXXXBITS+1 point to the same storage location ?


Thanks,
Ram Kumar