Help with Assembler code



High Level Assembler(HLASM) for MVS & VM & VSE

Re: Help with Assembler code

Postby enrico-sorichetti » Mon Nov 21, 2016 9:18 pm

if You look at the assembler listing ( the expansion of the instruction )
You will understand better what we are trying to tell You
cheers
enrico
When I tell somebody to RTFM or STFW I usually have the page open in another tab/window of my browser,
so that I am sure that the information requested can be reached with a very small effort
enrico-sorichetti
Global moderator
 
Posts: 3006
Joined: Fri Apr 18, 2008 11:25 pm
Has thanked: 0 time
Been thanked: 165 times

Re: Help with Assembler code

Postby Robert Sample » Mon Nov 21, 2016 9:30 pm

I havent understood this completely.Is it that X'00' and XXXXBITS+1 point to the same storage location ?
NO! When assembled, the code that is to be executed for the TM 0(R5),X'00') is X'91005000' -- 91 is the op code, 00 is the test byte, 5 is the register and 000 is the offset from the register. The X'91' is stored at location XXXXBITS, the X'00' at XXXXBITS+1, and the X'5000' at XXXXBITS+2 and +3. So if you change XXXXBITS+1, then you change -- during execution of the program -- the TM from looking at X'00' to whatever you changed the byte to.

These users thanked the author Robert Sample for the post:
ramkumar1992sp (Mon Nov 21, 2016 9:59 pm)
Robert Sample
Global moderator
 
Posts: 3720
Joined: Sat Dec 19, 2009 8:32 pm
Location: Dubuque, Iowa, USA
Has thanked: 1 time
Been thanked: 279 times

Re: Help with Assembler code

Postby ramkumar1992sp » Mon Nov 21, 2016 10:00 pm

Thanks Robert..That clarified my doubts.
ramkumar1992sp
 
Posts: 71
Joined: Sat Jul 23, 2016 8:52 am
Has thanked: 40 times
Been thanked: 0 time

Re: Help with Assembler code

Postby steve-myers » Mon Nov 21, 2016 10:16 pm

ramkumar1992sp wrote:Thanks Steve.

I see the instruction is modified using Register RB before the TM instruction is executed.This isn't a new program.It looks like it was written in 1972.

When the TM instruction is executed,aren't we checking the contents of RB register against the mask bits of zeroes.How is the value of XXXXBITS affecting it ?

LA    RC,XXXXBITS
---
---
NEWMEET  MVC   XXXXBITS+1(1),1(RB)  
-----
----
---
XXXXBITS TM    0(R5),X'00'          
         BC    5,SETCONFL          

 



Thanks,
Ram Kumar
No no, and no.
When the TM instruction is executed,aren't we checking the contents of RB register against the mask bits of zeroes.How is the value of XXXXBITS affecting it ?

Register 5 is an address. 0(5) directs the machine to compute an address by adding 0 to the contents of register 5. The contents of the mask in the instruction are then used to test the contents of the storage location specified by the address.

LA    RC,XXXXBITS

If register C is the program base register, as is often, though by no means always, true, the instruction is corrupting the register. The net effect is oops,

MVC   XXXXBITS+1(1),1(RB)

If this instruction is actually in your program and executed, the X'00' in the TM instruction is altered with the contents of a byte in storage whose address is computed by adding 1 to the contents of register B. This was poor programming in 1972, and is still poor programming.

You really need to hire someone who actually knows Assembler to correct your program. Trying to correct it using these forums will more likely than not foul it up worse. Me? I will not add to the confusion any more!

These users thanked the author steve-myers for the post:
ramkumar1992sp (Mon Nov 21, 2016 10:45 pm)
steve-myers
Global moderator
 
Posts: 2105
Joined: Thu Jun 03, 2010 6:21 pm
Has thanked: 4 times
Been thanked: 243 times

Previous

Return to Assembler

 


  • Related topics
    Replies
    Views
    Last post